Semiconductor integrated circuit and method for inspecting same

ABSTRACT

An internal connection output pad ( 14 A) connected to a CMOS output circuit ( 15 A,  16 A) on a first chip ( 11 A) is electrically connected via a chip-to-chip bonding wire ( 17 ) to an internal connection input pad ( 14 B) connected to a CMOS input circuit ( 15 B,  16 B) on a second chip ( 11 B). In order to inspect the presence or absence of leakage resistance ( 40 ), a test circuit ( 30 ) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad ( 14 A) via the CMOS output circuit ( 15 A,  16 A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

RELATED APPLICATIONS

This application is the U.S. National Phase under 35 U.S.C. §371 ofInternational Application No. PCT/JP2006/315385, filed on Aug. 3, 2006,which in turn claims the benefit of Japanese Application No.2006-047238, filed on Feb. 23, 2006, the disclosures of whichApplications are incorporated by reference herein.

TECHNICAL FIELD

The present invention relates to a technique of performing leakagecurrent measurement at a chip-to-chip internal connection pad that isnot externally exposed after sealing, with high precision, in asemiconductor integrated circuit including a plurality of chips that areenclosed in the same package.

BACKGROUND ART

In recent years, semiconductor integrated circuits called MCP (multichipin package) or MCM (multichip in module) in which a plurality of chipsare enclosed in the same package have been manufactured. A bonding padprovided on each chip is connected to an external terminal via a bondingwire, and also, wire bonding is performed between each chip.

If wire bonding is performed with respect to a chip that is charged withstatic electricity, electric charges may be released, so that a circuitin the vicinity of a pad may be damaged. When the circuit issignificantly damaged, the circuit no longer logically operates, so thatthe circuit can be detected as a defective product by a typical functiontest. However, when the damage on the circuit is not significant, thecircuit still logically normally operates, so that it is difficult todetect the circuit as a defective product by the function test. Inaddition, as is different from a bonding pad connected to an externalterminal, it is difficult to detect circuit damage occurring in thevicinity of a bonding pad for chip-to-chip internal connection.

There is a certain conventional technique of examining whether or notcircuit damage has occurred during wire bonding of a chip-to-chipinternal connection pad. In this technique, after an input pad on afirst chip is disconnected from an internal circuit of the first chip,an output pad on a second chip is set to be in a high (H) level outputstate or a low (L) level output state. By measuring a quiescent powersupply current (IDDS) in this state, the occurrence of a minute leakagecurrent in these internal connection pads is detected (see PatentDocument 1).

Patent Document 1: Japanese Unexamined Patent Application PublicationNo. 2002-131400

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

In recent years, as the miniaturization of manufacturing processes forsemiconductor integrated circuits has been advanced, the thresholdvoltage of a transistor needs to be decreased, so that IDDS tends toincrease. When IDDS increases, a minute leakage current due to circuitdamage in the vicinity of a pad is likely to be smaller than IDDS. Inthis case, a defective product cannot be correctly detected bymeasurement of IDDS.

Also, IDDS may be used to detect a leakage current at an internalconnection pad. In this case, a test circuit needs to be provided ineach of all chips enclosed in the same package. Therefore, for example,the number of parts mounted on a circuit board may be reduced byenclosing a conventional chip and a newly developed chip in the samepackage. In this case, a test circuit needs to be incorporated into theconventional chip, i.e., a change needs to be made in the conventionalchip.

An object of the present invention is to provide a semiconductorintegrated circuit in which a leakage current caused by chip-to-chipwire bonding can be easily and correctly detected without leading to anincrease in the number of test circuits, and a method for inspecting thesemiconductor integrated circuit.

Solution to the Problems

To achieve the object, the present invention provides a semiconductorintegrated circuit comprising a first chip and a second chip. The secondchip has an internal connection input pad, and a CMOS input circuitconnected to the internal connection input pad. The first chip has aninternal connection output pad electrically connected via a bonding wireto the internal connection input pad, a CMOS output circuit connected tothe internal connection output pad, and a test circuit for controlling,via the CMOS output circuit, a high-impedance (Hi-Z) output state, ahigh (H) level output state and a low (L) level output state of theinternal connection output pad.

The semiconductor integrated circuit is inspected as follow. A firstcurrent flowing through a path from a power supply to a ground ismeasured while the internal connection output pad is controlled to be ina high-impedance output state. A second current flowing through a pathfrom a power supply to a ground is measured while the internalconnection output pad is controlled to be in a high-level output state.A third current flowing through a path from a power supply to a groundwhile the internal connection output pad is controlled to be in alow-level output state. When leakage caused by chip-to-chip wire bondingoccurs on the ground side, the second current contains a minute leakagecurrent. When such leakage occurs on the power supply side, the thirdcurrent contains a minute leakage current. Also, the first, second andthird currents each contain a transistor leakage current. Therefore, ifa difference between the first current and the second current iscalculated and a difference between the first current and the thirdcurrent is calculated, the transistor leakage current is canceled, sothat a correct minute leakage current is detected. The presence orabsence of a defect is determined based on a magnitude of the minuteleakage current.

Effect of the Invention

According to the present invention, only a minute leakage current causedby chip-to-chip wire bonding can be correctly detected based on theresult of current measurement in each output state (Hi-Z, H-level,L-level) of an output pad, so that a deterioration in inspectionprecision caused by an increase in IDDS due to a decrease in thresholdvoltage of a transistor can be prevented. In addition, the state of anoutput pad is controlled via a CMOS output circuit on a first chip, sothat the configuration of a test circuit can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an exemplary configuration of asemiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a detailed exemplary configurationof a test circuit of FIG. 1.

FIG. 3 is a diagram showing an operation of the test circuit of FIG. 2.

FIG. 4 is a circuit diagram showing another exemplary configuration ofthe semiconductor integrated circuit of the present invention.

FIG. 5 is a circuit diagram showing a variation of a plurality of padoutputs of FIG. 4.

FIG. 6 is a circuit diagram showing a configuration of afrequency-division circuit in the test circuit for implementing thesemiconductor integrated circuit of FIG. 5.

FIG. 7 is a circuit diagram showing a configuration of an output levelcontrol signal generating circuit in the test circuit for implementingthe semiconductor integrated circuit of FIG. 5.

FIG. 8 is a circuit diagram showing a configuration of a pad outputcontrol signal generating circuit in the test circuit for implementingthe semiconductor integrated circuit of FIG. 5.

FIG. 9 is a timing chart showing an operation of the test circuit havingthe configurations of FIGS. 6 to 8.

FIG. 10 is a circuit diagram showing still another exemplaryconfiguration of the semiconductor integrated circuit of the presentinvention.

DESCRIPTION OF THE REFERENCE CHARACTERS

10 semiconductor integrated circuit

11A first chip

11B second chip

12A, 12B power supply pad

13A, 13B ground pad

14A, 14B internal connection pad

14A1 to 14An internal connection pad (output pad)

14B1 to 14Bn internal connection pad (input pad)

15A, 15B P-channel MOS transistor

16A, 16B N-channel MOS transistor

17 chip-to-chip bonding wire

171 to 17 n chip-to-chip bonding wire

21A, 21B bonding wire

22, 22A, 22B external terminal (power supply terminal)

23A, 23B ammeter

24A, 24B bonding wire

25, 25A, 25B external terminal (ground terminal)

26A, 26B ammeter

30 test circuit

31, 32, 33 test pad

40, 41, 42 leakage resistance

51A, 51B tri-state buffer

52A, 52B input buffer

200 frequency-division circuit

250 output level control signal generating circuit

300 pad output control signal generating circuit

C1 output impedance control signal

C2 output level control signal

C21 to C24 output level control signal

CK clock signal

IN internal input signal

OUT internal output signal

OUTCA, OUTCB buffer output control signal

OUTP, OUTN pad output control signal

OUTP1 to OUTP4 pad output control signal

OUTN1 to OUTN4 pad output control signal

PAD pad output

PAD1 to PADn pad output

TE test enable signal

VDDA, VDDB power supply

VSSA, VSSB ground

BEST MODE FOR CARRYING OUTPUT THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings.

FIG. 1 shows an exemplary configuration of a semiconductor integratedcircuit according to the present invention. The semiconductor integratedcircuit 10 of FIG. 1 includes a first chip 11A and a second chip 11B.

The first chip 11A has a power supply pad 12A, a ground pad 13A, anoutput pad 14A for internal connection, a P-channel MOS transistor 15A,and an N-channel MOS transistor 16A. The source and drain of theP-channel MOS transistor 15A are connected to the power supply pad 12Aand the internal connection output pad 14A, respectively. The source anddrain of the N-channel MOS transistor 16A are connected to the groundpad 13A and the internal connection output pad 14A, respectively.

The second chip 11B has a power supply pad 12B, a ground pad 13B, aninput pad 14B for internal connection, a P-channel MOS transistor 15B,and an N-channel MOS transistor 16B. The gate and source of theP-channel MOS transistor 15B are connected to the internal connectioninput pad 14B and the power supply pad 12B, respectively. The gate andsource of the N-channel MOS transistor 16B are connected to the internalconnection input pad 14B and the ground pad 13B, respectively.

The internal connection output pad 14A on the first chip 11A iselectrically connected via a chip-to-chip bonding wire 17 to theinternal connection input pad 14B on the second chip 11B. The P-channelMOS transistor 15A and the N-channel MOS transistor 16A on the firstchip 11A constitute a CMOS output circuit that is connected to theinternal connection input pad 14B. The P-channel MOS transistor 15B andthe N-channel MOS transistor 16B on the second chip 11B constitute aCMOS input circuit that is connected to the internal connection inputpad 14B, and the drains of these transistors are connected together sothat an internal input signal IN is supplied to an internal circuit (notshown) of the second chip 11B.

The first chip 11A further has a test circuit 30 for controlling a Hi-Zoutput state, an H-level output state and an L-level output state of theinternal connection output pad 14A via the CMOS output circuit (15A,16A), and test pads 31, 32 and 33. The test circuit 30 receives aninternal output signal OUT from an internal circuit (not shown) of thefirst chip 11A and receives a test enable signal TE, an output impedancecontrol signal C1, and an output level control signal C2 from theoutside via the test pads 31, 32 and 33, respectively, and supplies padoutput control signals OUTP and OUTN to the gates of the P-channel MOStransistor 15A and the N-channel MOS transistor 16A, respectively.

The semiconductor integrated circuit 10 of FIG. 1 further has first,second, third and fourth external terminals 22A, 22B, 25A and 25B. Thefirst external terminal 22A, which is a power supply terminal of thefirst chip 11A, is connected via a bonding wire 21A to the power supplypad 12A on the first chip 11A. The second external terminal 22B, whichis a power supply terminal of the second chip 11B, is connected to abonding wire 21B to the power supply pad 12B on the second chip 11B. Thethird external terminal 25A, which is a ground terminal of the firstchip 11A, is connected via a bonding wire 24A to the ground pad 13A onthe first chip 11A. The fourth external terminal 25B, which is a groundterminal of the second chip 11B, is connected via a bonding wire 24B tothe ground pad 13B on the second chip 11B.

When the semiconductor integrated circuit 10 of FIG. 1 is inspected, thefirst external terminal 22A is connected via a first ammeter 23A to apower supply VDDA, the second external terminal 22B is connected via asecond ammeter 23B to a power supply VDDB, and the third externalterminal 25A is connected via a third ammeter 26A to a ground VSSA, andthe fourth external terminal 25B is connected via a fourth ammeter 26Bto a ground VSSB. TE, C1 and C2 are supplied to the test pads 31, 32 and33 by contacting probe needles to these pads. Note that, as long as aconstraint on the number of external terminals is satisfied, the testpads 31, 32 and 33 may be connected via bonding wires to the respectiveexternal terminals so as to enable inspection after sealing the package.

In FIG. 1, it is assumed that when wire bonding is performed betweenboth the chips 11A and 11B, leakage resistance 40 occurs between theinternal connection output pad 14A and the ground pad 13A on the firstchip 11A. In FIG. 1, “PAD” represents a pad output (voltage) of theinternal connection output pad 14A.

FIG. 2 shows a detailed exemplary configuration of the test circuit 30of FIG. 1. The test circuit 30 of FIG. 2 includes five AND gates 101,102, 103, 104 and 105, three OR gates 106, 107 and 108, and twoinverters 109 and 110. The signal line TE is connected via a pull-downresistor 111 to the ground.

FIG. 3 shows an operation of the test circuit 30 of FIG. 2. During anormal operation of the semiconductor integrated circuit 10 of FIG. 1,TE is set to be “L” by the pull-down resistor 111 (TE=“L”). In thiscase, a level of the pad output PAD is controlled to be “H” or “L” onlyby OUT irrespective of C1 and C2. In other words, the P-channel MOStransistor 15A and the N-channel MOS transistor 16A on the first chip11A operate as a CMOS inverter. During inspection of the semiconductorintegrated circuit 10 of FIG. 1, TE is set to be “H” (TE=“H”). If TE=“H”and C1=“H”, the pad output PAD is in the Hi-Z state irrespective of C2and OUT. Also, if TE=“H” and C1=“L”, the level of the pad output PAD iscontrolled to be “H” or “L” only by C2 irrespective of OUT.

Referring back to FIG. 1, a method for inspecting the presence orabsence of the leakage resistance 40 will be described. Initially, whilethe internal connection output pad 14A is controlled to be in the Hi-Zoutput state by the test circuit 30, first current measurement isperformed using the first to fourth ammeters 23A, 23B, 26A and 26B. Inthis case, since OUTP=“H” and OUTN=“L”, the P-channel MOS transistor 15Aand the N-channel MOS transistor 16A on the first chip 11A are both inthe OFF state. Either the P-channel MOS transistor 15B or the N-channelMOS transistor 16B on the second chip 11B is in the OFF state at anytime irrespective of the presence or absence of the leakage resistance40. Even if the leakage resistance 40 is present, a current does notflow through the leakage resistance 40. Therefore, only a transistorleakage current can be measured by any of the first to fourth ammeters23A, 23B, 26A and 26B.

Next, while the internal connection output pad 14A is controlled to bein the H-level output state by the test circuit 30, second currentmeasurement is performed using the first to fourth ammeters 23A, 23B,26A and 26B. In this case, since OUTP=“L” and OUTN=“L”, the P-channelMOS transistor 15A is in the ON state and the N-channel MOS transistor16A is in the OFF state on the first chip 11A. Either the P-channel MOStransistor 15B or the N-channel MOS transistor 16B is in the OFF stateat any time on the second chip 11B. Therefore, when the leakageresistance 40 illustrated is not present, only a transistor leakagecurrent can be measured by any of the first to fourth ammeters 23A, 23B,26A and 26B. When the leakage resistance 40 is present between theinternal connection output pad 14A and the ground pad 13A on the firstchip 11A as illustrated, a minute leakage current flows through theleakage resistance 40, so that a superimposition of a transistor leakagecurrent and the minute leakage current is measured by the first ammeter23A and the third ammeter 26A. Here, if a difference between the resultof the first current measurement and the result of the second currentmeasurement in the first ammeter 23A or the third ammeter 26A iscalculated, the transistor leakage current is canceled to detect acorrect minute leakage current, so that the presence of the leakageresistance 40 is found.

Similarly, when leakage resistance is present between the internalconnection input pad 14B and the ground pad 13B on the second chip 11B,then if a difference between the result of the first current measurementand the result of the second current measurement in the first ammeter23A or the fourth ammeter 26B is calculated, a transistor leakagecurrent is canceled to detect a correct minute leakage current, so thatthe presence of the leakage resistance is found.

When leakage resistance is present between the internal connectionoutput pad 14A and the power supply pad 12A on the first chip 11A, thirdcurrent measurement is performed using the first to fourth ammeters 23A,23B, 26A and 26B while the internal connection output pad 14A iscontrolled to be in the L-level output state by the test circuit 30. Ifa difference between the result of the first current measurement and theresult of the third current measurement in the first ammeter 23A or thethird ammeter 26A is calculated, a transistor leakage current iscanceled to detect a correct minute leakage current, so that thepresence of the leakage resistance is found. Similarly, when leakageresistance is present between the internal connection input pad 14B andthe power supply pad 12B on the second chip 11B, then if a differencebetween the result of the first current measurement and the result ofthe third current measurement in the second ammeter 23B or the thirdammeter 26A is calculated, a transistor leakage current is canceled todetect a correct minute leakage current, so that the presence of theleakage resistance is found.

As described above, in the semiconductor integrated circuit 10 of FIG.1, only a minute leakage current caused by chip-to-chip wire bonding canbe correctly detected based on the result of the current measurement ineach output state (Hi-Z, H-level, L-level) of the internal connectionoutput pad 14A, so that a deterioration in inspection precision causedby an increase in IDDS due to a decrease in threshold voltage of atransistor can be prevented.

Note that when the first and second external terminals 22A and 22B areintegrated into a single external terminal, an ammeter may be connectedto the single external terminal and a current flowing in from a singlepower supply may be measured using the ammeter. Also, when the third andfourth external terminals 25A and 25B are integrated into a singleexternal terminal, an ammeter may be connected to the single externalterminal and a current flowing out to a single ground may be measuredusing the ammeter.

When the first chip 11A has a plurality of internal connection outputpads and the second chip 11B has a plurality of internal connectioninput pads, and the first chip 11A and the second chip 11B areelectrically connected via a plurality of bonding wires, then if the padoutput control signals OUTP and OUTN output from the test circuit 30 aredistributed to CMOS output circuits connected to the internal connectionoutput pads, the high-impedance output states, high-level output statesand low-level output states of the internal connection output pads canbe controlled via the CMOS output circuits, so that only a minuteleakage current caused by chip-to-chip wire bonding can be correctlydetected as is similar to that described above. Note that since all padoutputs have the same phase, a leakage current between bonding wirescannot be detected.

FIG. 4 shows another exemplary configuration of the semiconductorintegrated circuit 10 of the present invention. In FIG. 4, a first chip11A has n internal connection output pad 14A1 to 14An and a second chip11B has n internal connection input pads 14B1 to 14Bn, where n is aninteger of two or more, and the first chip 11A and the second chip 11Bare electrically connected via n bonding wires 171 to 17 n. A firstexternal terminal 22 is a common power supply terminal shared by thefirst chip 11A and the second chip 11B, and a second external terminal25 is a common ground terminal shared by the first chip 11A and thesecond chip 11B. In FIGS. 4, 41 and 42 represent leakage resistanceoccurring between bonding wires. Note that, for the sake of simplicity,CMOS output circuits connected to the internal connection output pads14A1 to 14An and CMOS input circuits connected to the internalconnection input pads 14B1 to 14Bn are not shown in FIG. 4. Also, a testcircuit for controlling states of the internal connection output pads14A1 to 14An via the CMOS output circuits is not shown.

According to FIG. 4, the test circuit controls n pad outputs PAD1 toPADn so that the H-level output state and the L-level output state arealternated between adjacent pads. Thereby, the presence of the leakageresistance 41 and 42 between bonding wires can be found. Note that it isnot possible to identify the bonding wire in which leakage occurs.

FIG. 5 shows a variation of the n pad outputs PAD1 to PADn of FIG. 4. InFIG. 5, a test circuit controls the n pad outputs PAD1 to PADn so thatonly a particular pad output (e.g., PAD2) has an output state (e.g., theL-level output state) having a phase opposite to that of the other padoutputs. Thereby, the location of the leakage resistance 41 betweenbonding wires can also be found.

Next, a test circuit will be described that has a function ofsuccessively switching the n pad outputs PAD1 to PADn to the L-leveloutput state so as to facilitate the detection of leakage resistancebetween bonding wires.

FIGS. 6, 7 and 8 show exemplary configurations of a test circuit havingsuch a function, where n=4. FIG. 6 is a circuit diagram showing aconfiguration of a frequency-division circuit 200. FIG. 7 is a circuitdiagram showing a configuration of an output level control signalgenerating circuit 250. FIG. 8 is a circuit diagram showing aconfiguration of a pad output control signal generating circuit 300.

The frequency-division circuit 200 of FIG. 6 includes three D flip-flops201, 202 and 203 so as to divide the frequency of a clock signal CK andsupply five signals D0, D1, D1B, D2 and D2B to the output level controlsignal generating circuit 250.

The output level control signal generating circuit 250 of FIG. 7includes four NOR gates 251, 252, 253 and 254 and four AND gates 255,256, 257 and 258 so as to generate output level control signals C21,C22, C23 and C24 for respective pads corresponding to C2.

The pad output control signal generating circuit 300 of FIG. 8 includesunit circuits 301, 302, 303 and 304 for respective pads, each of whichhas a configuration similar to that of the test circuit 30 of FIG. 2,and a single inverter 109, so as to generate pad output control signalsOUTP1, OUTN1, OUTP2, OUTN2, OUTP3, OUTN3, OUTP4 and OUTN4. The unitcircuits 301, 302, 303 and 304 receive internal output signals OUT1,OUT2, OUT3 and OUT4 from an internal circuit (not shown), respectively,and a common output impedance control signal C1. Note that the pull-downresistor of a signal line TE is not shown in FIG. 8.

FIG. 9 shows an operation of the test circuit having the configurationsof FIGS. 6 to 8. It can be seen from FIG. 9 that the four pad outputsPAD1 to PAD4 are successively switched to the L-level output state.

FIG. 10 shows still another exemplary configuration of the semiconductorintegrated circuit 10 of the present invention. In FIG. 10, a first chip11A has a tri-state buffer 51A, an input buffer 52A, and an internalconnection pad 14A, and a second chip 11B has a tri-state buffer 51B, aninput buffer 52B, and an internal connection pad 14B. In the first chip11A, the output of the tri-state buffer 51A and the input of the inputbuffer 52A are connected to the internal connection pad 14A. Similarly,in the second chip 11B, the output of the tri-state buffer 51B and theinput of the input buffer 52B are connected to the internal connectionpad 14B. The internal connection pad 14A on the first chip 11A iselectrically connected via a chip-to-chip bonding wire 17 to theinternal connection pad 14B on the second chip 11B. The four buffers51A, 52A, 51B and 52B all have CMOS configurations. OUTCA and OUTCB arebuffer output control signals for controlling the outputs of thetri-state buffers 51A and 51B to be in the Hi-Z output state,respectively.

According to FIG. 10, a signal can be transferred from the tri-statebuffer 51A on the first chip 11A to the input buffer 52B on the secondchip 11B, and a signal can be transferred from the tri-state buffer 51Bon the second chip 11B to the input buffer 52A on the first chip 11A. Inother words, bidirectional communication can be performed between boththe chips 11A and 11B. When the internal connection pad 14A on the firstchip 11A functions as an output pad, the internal connection pad 14B onthe second chip 11B functions as an input pad. When the internalconnection pad 14B on the second chip 11B functions as an output pad,the internal connection pad 14A on the first chip 11A functions as aninput pad.

In order to inspect chip-to-chip wire bonding, the first chip 11A ofFIG. 10 includes a test circuit (not shown) that controls the Hi-Zoutput state, H-level output state and L-level output state of theinternal connection pad 14A. In addition, during an operation of thetest circuit, the output of the tri-state buffer 51B on the second chip11B is controlled to be in the Hi-Z output state. Therefore, as in thecase of FIG. 1, only a minute leakage current caused by chip-to-chipwire bonding can be correctly detected based on the result of currentmeasurement in each output state (Hi-Z, H-level, L-level) of theinternal connection pad 14A.

Note that the present invention is applicable to a semiconductorintegrated circuit including three or more chips.

INDUSTRIAL APPLICABILITY

As described above, in the semiconductor integrated circuit of thepresent invention, a leakage current caused by chip-to-chip wire bondingcan be easily and correctly detected without leading to an increase inthe number of test circuits, and therefore, is useful as an LSI or thelike having a configuration in which a plurality of chips are enclosedin the same package.

1. A semiconductor integrated circuit comprising a first chip and asecond chip, wherein the second chip has: an internal connection inputpad; and a CMOS input circuit connected to the internal connection inputpad, and the first chip has: an internal connection output padelectrically connected via a bonding wire to the internal connectioninput pad; a CMOS output circuit connected to the internal connectionoutput pad, and a test circuit for controlling, via the CMOS outputcircuit, an output state of the internal connection output pad such thatthe output state of the internal connection output pad is controlled tobe in each of a high-impedance output state, a high-level output stateand a low-level output state, so that a current flowing through a pathfrom a power supply to a ground of the first chip or of the second chipis measured by a ammeter.
 2. The semiconductor integrated circuit ofclaim 1, wherein the internal connection input pad is also used as anoutput pad for a signal from the second chip to the first chip, and theinternal connection output pad is also used as an input pad for a signalfrom the second chip to the first chip.
 3. A semiconductor integratedcircuit comprising a first chip and a second chip, wherein the secondchip has: a plurality of internal connection input pads; and a pluralityof CMOS input circuits connected to the plurality of internal connectioninput pads, and the first chip has: a plurality of internal connectionoutput pads electrically connected via bonding wires to the plurality ofinternal connection input pads, respectively; a plurality of CMOS outputcircuits connected to the plurality of internal connection output pads,respectively; and a test circuit for controlling, via the plurality ofCMOS output circuits, output states of the internal connection outputpads such that the output states of the plurality of internal connectionoutput pads are each controlled to be in each of a high-impedance outputstate, a high-level output state and a low-level output state, so that acurrent flowing through a path from a power supply to a ground of thefirst chip or of the second chip is measured by an ammeter.
 4. Thesemiconductor integrated circuit of claim 3, wherein the test circuithas a function of controlling the plurality of internal connectionoutput pads so that the high-level output state and the low-level outputstate are alternated between adjacent pads.
 5. The semiconductorintegrated circuit of claim 3, wherein the test circuit has a functionof controlling the plurality of internal connection output pads so thatonly a particular pad has an output state having a phase opposite tothat of the other pads.
 6. The semiconductor integrated circuit of claim5, wherein the test circuit has a function of successively switching theplurality of internal connection output pads to the opposite-phaseoutput state.